Field
This disclosure relates to the field of data processing systems. More particularly, this disclosure relates to errors arising in the transmission of transactions via interconnect circuitry between one or more transaction masters and one or more transaction slaves.
Description
It is known to provide interconnect circuitry with mechanisms which generate and then check error detection codes (EDC), such as parity, applied to data and addresses passed across interconnect circuitry as part of transactions between transaction masters and transaction slaves. Such error correction codes may be used to detect, and potentially correct, errors arising in the data and address values which are transmitted.
Another source of error in such systems is that the control of the transmission of the transactions, as distinct from the content of the transactions themselves, may be subject to error. As an example, the interconnect circuitry may include many multiplexers and a single bit upset for a control signal to such a multiplexer may result in a transaction being routed to the wrong master or the wrong slave. Within systems where data integrity is important (e.g. safety critical systems), it is desirable that such errors in the control of transmission of transactions should at least be detected.
One possible approach to dealing with detecting errors in the control of transmission of transactions would be to provide a duplicate instance of the interconnect circuitry and operate this in lockstep with the primary interconnect circuitry. This would permit the outputs of the two instances of the interconnect circuitry to be compared and any difference would indicate an error within the interconnect circuitry. A disadvantage with such an approach would be the significant additional overhead associated with providing duplicate interconnect circuitry and comparators. Such duplicate interconnect circuitry and comparators would increase the circuit area, cost and power consumption of the data processing system.